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| DA C Austin Semiconductor, Inc. 10 Bit, 40MHz Current -Output DACs FEATURES * +2.7V to +3.3V Single-Supply Operation AS5181 PIN ASSIGNMENT (Top View) 24-Pin Flat Pack (F) * Wide Spurious-Free Dynamic Range: 70dB at fOUT = 2.2MHz * Fully Differential Output * Low-Current Standby or Full Shutdown Modes * Internal +1.2V, Low-Noise Bandgap Reference * Small 24-Pin Flat-pack Package OPTIONS * Package(s) 24-Pin Flat-pack * Operating Temperature Ranges Extended Temperature (-55oC to +125oC) Industrial Temperature (-40C to +85C) Military Processing (-55C to +125C) Space Processing (-55oC to +125oC) MARKING F XT IT MIL SPACE GENERAL DESCRIPTION The AS5181 is a 10-bit, current-output digital-to-analog converter (DAC) designed for superior performance in signal reconstruction or arbitrary waveform generation applications requiring analog signal reconstruction with low distortion and low-power operation. The AS5181 are designed for a 10pVs glitch operation to minimize unwanted spurious signal components at the output. An on-board 1.2V bandgap circuit provides a well-regulated, low-noise reference that can be disabled for external reference operation. The devices are designed to provide a high level of signal integrity for the least amount of power dissipation. They operate from a single 2.7V to 3.3V supply. Additionally, these DACs have three modes of operation: normal, low-power standby, and full shutdown, which provides the lowest possible power dissipation with a 1A (max) shutdown current. A fast wake-up time (0.5s) from standby mode to full DAC operation facilitates power conservation by activating the DAC only when required. For more products and information please visit our web site at www.austinsemiconductor.com AS5181 Rev. 0.3 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 DA C Austin Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS* AVDD, DVDD to AGND, DGND......................................-0.3V to +6V Digital Inputs to DGND..................................................-0.3V to +6V OUTP, OUTN, CREF to AGND.....................................-0.3V to +6V VREF to AGND..................................................................-0.3V to +6V AGND to DGND.............................................................-0.3V to +0.3V AVDD to DVDD ..............................................................................3.3V Maximum Current to Any Pin....................................................50mA Continuous Power Dissipation (TA = +70C) 24-Pin Flatpack (derate 9.50mW/C above +70C) .............762mW Storage Temperature Range .....................................-65C to +150C AS5181 Lead Temperature (soldering, 10s) .........................................+300C *Stresses at or greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods will affect reliability. ELECTRICAL CHARACTERISTICS (AVDD = DVDD = +3V 10%, AGND = DGND = 0, fCLK = 40MHz, IFS = 1mA, 400 differential output, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER STATIC PERFORMANCE Resolution Intergral Nonlinearity Differential Nonlinearity Zero-Scale Error Full-Scale Error DYNAMIC PERFORMANCE Output Settling Time Glitch Impulse CONDITION SYM N INL DNL MIN 10 -2 -1 -2 -40 TYP MAX UNITS Bits LSB LSB LSB LSB ns pVs Guaranteed monotonic 0.5 0.5 15 25 10 72 +2 1 +2 +40 To 0.5LSB error band fOUT = 550kHz Spurious-Free Dynamic Range to Nyquist fCLK = 40MHz TA = +25C fOUT = 2.2MHz fOUT = 550kHz SFDR 57 70 dBc -70 THD -68 -63 dB Total Harmonic Distortion to Nyquist fCLK = 40MHz TA = +25C fOUT = 2.2MHz fOUT = 550kHz 61 SNR 56 59 50 10 VFS 400 -0.3 -1 IFS RL 0.5 1 400 0.8 1 1.5 nVs pA/Hz mV V A mA dB Signal-to-Noise Ratio to Nyquist fCLK = 40MHz TA = +25C fOUT = 2.2MHz Clock and Data Feedthrough Output Noise ANALOG OUTPUT Full-Scale Output Voltage Voltage Compliance of Output Output Leakage Current Full-Scale Output Current DAC External Output Resistor Load AS5181 Rev. 0.3 6/05 All 0s to all 1s DACEN = 0 (continued) Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 DA C Austin Semiconductor, Inc. AS5181 ELECTRICAL CHARACTERISTICS (AVDD = DVDD = +3V 10%, AGND = DGND = 0, fCLK = 40MHz, IFS = 1mA, 400 differential output, CL = 5pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (continued) PARAMETER REFERENCE Output Voltage Range Output Voltage Temperature Drift Reference Output Drive Capability Reference Supply Rejection Current Gain (IFS/IREF) CONDITION SYM VREF TCVREF IREFOUT MIN 1.12 TYP 1.2 50 10 0.5 8 AVDD PD = 0, DACEN = 1, digital inputs at 0 or DVDD IAVDD DVDD PD = 0, DACEN = 1, digital inputs at 0 or DVDD PD = 0, DACEN = 1, digital inputs at 0 or DVDD PD = 1, DACEN = X, digital inputs at 0 or DVDD (X = don't care) IDVDD ISTANDBY ISHDN VIH VIL VIN = 0 or DVDD IIN CIN tDS tDH 10 0 5 5 0.5 50 tCLK tCH tCL 25 10 10 10 2 0.8 1 2.7 4.2 1 0.5 2.7 1.7 3.3 4.0 3.3 5.0 1.5 1 MAX 1.28 UNITS V ppm/C A mV/V mA/mA V mA V mA mA A POWER REQUIREMENTS Analog Power-Supply Voltage Analog Supply Current Digital Power-Supply Voltage Digital Supply Current Standby Current Shutdown Current LOGIC INPUTS AND OUTPUT Digital Input Voltage High Digital Input Voltage Low Digital Input Current Digital Input Capacitance TIMING CHARACTERISTIC DAC DATA to CLK Rise Setup Time DAC CLK Rise to DATA Hold Time CS\ Fall to CLK Rise Time CS\ Fall to CLK Fall Time DACEN Rise Time to VOUT PD Fall Time to VOUT Clock Period Clock High Time Clock Low Time V V A pF ns ns ns ns s s ns ns ns AS5181 Rev. 0.3 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 DA C Austin Semiconductor, Inc. AS5181 TYPICAL OPERATING CHARACTERISTICS (AVDD = DVDD = +3V, AGND = DGND = 0, IFS = 1mA, 400 differential output, CL = 5pF, TA = +25C, unless otherwise noted.) AS5181 Rev. 0.3 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 DA C Austin Semiconductor, Inc. AS5181 TYPICAL OPERATING CHARACTERISTICS (AVDD = DVDD = +3V, AGND = DGND = 0, IFS = 1mA, 400 differential output, CL = 5pF, TA = +25C, unless otherwise noted.) (continued) AS5181 Rev. 0.3 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 DA C Austin Semiconductor, Inc. AS5181 TYPICAL OPERATING CHARACTERISTICS (AVDD = DVDD = +3V, AGND = DGND = 0, IFS = 1mA, 400 differential output, CL = 5pF, TA = +25C, unless otherwise noted.) (continued) AS5181 Rev. 0.3 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 DA C Austin Semiconductor, Inc. PIN DESCRIPTION PIN 1 2 3 4 5 NAME CREF OUTP OUTN AGND AVDD FUNCTION REFO Positive Analog Output, Current Output Negative Analog Output, Current Output Analog Ground Analog Positive Supply, +2.7V to +3.3V AS5181 6 DAC Enable, Digital Input 0: Enter DAC standby mode with PD = DGND DACEN 1: Power-up DAC with PD = DGND X: Enter shutdown mode with PD = DV DD (X = Don't Care) Power-Down Select 0: Enter DAC standby mode (DACEN = DGND) or power-up DAC (DACEN = DV DD ) PD 1: Enter shutdown mode CS\ Active-Low Chip Select CLK Clock Input REN\ Active-Low Reference Enable. Connect to DGND to activate on-chip +1.2V reference. D0 Data Bit D0 (LSB) D1 - D8 Data Bits D1 - D8 D9 Data Bit D9 (MSB) DV DD DGND REFR REFO Digital Supply, +2.7V to +3.3V Digital Ground Reference Input Reference Output 7 8 9 10 11 12 - 19 20 21 22 23 24 AS5181 Rev. 0.3 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 DA C Austin Semiconductor, Inc. DETAILED DESCRIPTION The AS5181 is a 10-bit digital-to-analog converters (DACs) capable of operating with clock speeds up to 40MHz. Each converter consists of separate input and DAC registers, followed by a current source array capable of generating up to 1.5mA full-scale output current (Figure 1). An integrated 1.2V voltage reference and control amplifier determine the data converters' full-scale output currents/voltages. Careful reference design ensures close gain matching and excellent drift characteristics. AS5181 selected and provides a +1.2V output. Due to its limited 10A output drive capability, REFO must be buffered with an external amplifier, if heavier loading is required. The AS5181 also employ a control amplifier designed to regulate simultaneously the full-scale output current (IFS) for both outputs of the devices. The output current is calculated as follows: IFS = 8 . IREF where IREF is the reference output current (IREF = VREFO/RSET) and IFS is the full-scale output current. RSET is the reference resistor that determines the amplifier's output current on the AS5181 (Figure 2). This current is mirrored into the current source array, where it is equally distributed between matched current segments and summed to valid output current readings for the DACs. Internal Reference and Control Amplifier The AS5181 provide an integrated 50ppm/C, 1.2V, low-noise bandgap reference that can be disabled and overridden by an external reference voltage. REFO serves either as an external reference input or an integrated reference output. If REN\ is connected to DGND, the internal reference is FIGURE 1: Functional Diagram AS5181 Rev. 0.3 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 DA C Austin Semiconductor, Inc. External Reference To disable the AS5181 internal reference, connect REN\ to DVDD. A temperature-stable, external reference may now be applied to drive the REFO pin to set the full-scale output (Figure 3). Choose a reference capable of supplying at least 150A to drive the bias circuit that generates the cascode current for the current array. For improved accuracy and drift performance, choose a fixed output voltage reference. AS5181 and current array are inactive and the DAC supply current is reduced to 1A. To enter this mode, connect PD to DVDD. To return to active mode, connect PD to DGND and DACEN to DVDD. About 50s are required for the parts to leave shutdown mode and settle to their outputs' values prior to shutdown. The "Power-Down Mode Selection" table lists the power-down mode selection. Timing Information Standby Mode To enter the lower-power standby mode, connect digital inputs PD and DACEN to DGND. In standby, both the reference and the control amplifier are active with the current array inactive. To exit this condition, DACEN must be pulled high with PD held at DGND. The AS5181 typically require 50s to wake up and let both outputs and the reference settle. Figure 4 shows a detailed timing diagram for the AS5181. With each high transition of the clock, the input latch is loaded with the digital value set by bits D9 through D0. The content of the input latch is then shifted to the DAC register, and the output updates at the rising edge of the next clock. Outputs The AS5181 output is designed to supply full-scale output currents of 1mA into 400 loads in parallel with a capacitive load of 5pF. Shutdown Mode For lowest power consumption, the AS5181 provide a power-down mode in which the reference, control amplifier, FIGURE 2: Setting IFS with the Internal +1.2V Reference and the Control Amplifier AS5181 Rev. 0.3 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 DA C Austin Semiconductor, Inc. POWER-DOWN MODE SELECTION PD DACEN POWER-DOWN MODE OUTPUT STATE (POWER-DOWN SELECT) (DAC ENABLE) 0 0 Standby High-Z 0 1 Wake-Up Last state prior to standby mode 1 X Shutdown High-Z AS5181 X = Don't Care FIGURE 3: AS5181 with External Reference APPLICATIONS INFORMATION Static and Dynamic Performance Definitions Integral Nonlinearity Integral nonlinearity (INL) (Figure 5a) is the deviation of the values on an actual transfer function from either a beststraight-line fit (closest approximation to the actual transfer curve) or a line drawn between the endpoints of the transfer function once offset and gain errors have been nullified. For a DAC, the deviations are measured every single step. Offset Error Offset error (Figure 5c) is the difference between the ideal and the actual offset point. For a DAC, the offset point is the step value when the digital input is zero. This error affects all codes by the same amount and can usually be compensated by trimming. Gain Error Gain error (Figure 5d) is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. Differential Nonlinearity Differential nonlinearity (DNL) (Figure 5b) is the difference between an actual step height and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function. AS5181 Rev. 0.3 6/05 Settling Time Settling time is the amount of time required from the start of a transition until the DAC output settles its new output value to within the converter's specified accuracy. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 10 DA C Austin Semiconductor, Inc. Digital Feedthrough Digital feedthrough is the noise generated on a DAC's output when any digital input transitions. Proper board layout and grounding will significantly reduce this noise, but there will always be some feedthrough caused by the DAC itself. AS5181 Differential to Single-Ended Conversion A low-distortion, high-input bandwidth amplifier may be used to generate a voltage from the array current output of the AS5181. The differential voltage across OUTP and OUTN is converted into a single-ended voltage by designing an appropriate operational amplifier configuration (Figure 6). Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the input signal's first four harmonics to the fundamental itself. This is expressed as: I/Q Reconstruction in a QAM Application The low-distortion performance of two AS5181s supports analog reconstruction of in-phase (I) and quadrature (Q) carrier components typically used in quadrature amplitude modulation (QAM) architectures where two separate buses carry the I and Q data. A QAM signal is both amplitude (AM) and phase modulated, created by summing two independently modulated carriers of identical frequency but different phase (90 phase difference). In a typical QAM application (Figure 7), the modulation occurs in the digital domain, and two DACs such as the AS5181 may be used to reconstruct the analog I and Q components. The I/Q reconstruction system is completed by a quadrature modulator that combines the reconstructed components with in-phase and quadrature carrier frequencies and then sums both outputs to provide the QAM signal. where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component. FIGURE 4: TIMING DIAGRAM AS5181 Rev. 0.3 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 11 DA C Austin Semiconductor, Inc. Using the AS5181 for Arbitrary Waveform Generation Designing a traditional arbitrary waveform generator (AWG) requires five major functional blocks (Figure 8a): clock generator, counter, waveform memory, DAC for waveform reconstruction, and output filter. The waveform memory contains the sequentially stored digital replica of the desired analog waveforms. This memory shares a common clock with the DAC. For each clock cycle, a counter adds one count to the address for the waveform memory. The memory then loads the next value to the DAC, which generates an analog output voltage corresponding to that data value. A DAC output filter can either be a simple or complex lowpass filter, depending on the AWG requirements for waveform function and frequencies. The main limitations of the AWG's flexibility are DAC AS5181 resolution and dynamic performance, memory length, clock frequency, and the filter characteristics. Although the AS5181 offer high-frequency operation and excellent dynamics, they are suitable for relaxed requirements in resolution (10-bit AWGs). To increase an AWG's highfrequency accuracy, temperature stability, wide-band tuning, and past phase-continuous frequency switching, the user may approach a direct digital synthesis (DDS) AWG (Figure 8b). This DDS loop supports standard waveforms that are repetitive, such as sine, square, TTL, and triangular waveforms. DDS allows for precise control of the data-stream input to the DAC. Data for one complete output waveform cycle is sequentially stored in a RAM. As the RAM addresses are changing, the DAC converts the incoming data bits into a corresponding voltage waveform. The resulting output signal frequency is proportional to the frequency rate at which the RAM addresses are changed. FIGURES 5 A thru D AS5181 Rev. 0.3 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 12 DA C Austin Semiconductor, Inc. FIGURE 6: Differential to Single-Ended Conversion Using a Low-Distortion Amplifier AS5181 FIGURE 7: Using the AS5181 for I/Q Signal Reconstruction AS5181 Rev. 0.3 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 13 DA C Austin Semiconductor, Inc. Grounding and Power-Supply Decoupling Grounding and power-supply decoupling strongly influence the AS5181's performance. Unwanted digital crosstalk may couple through the input, reference, power-supply, and ground connections, which may affect dynamic specifications like SNR or SFDR. In addition, electromagnetic interference (EMI) can either couple into or be generated by the AS5181. Therefore, grounding and power-supply decoupling guidelines for high-speed, high-frequency applications should be closely followed. First, a multilayer PC board with separate ground and power-supply planes is recommended. High-speed signals should be run on controlled impedance lines directly above the ground plane. Since the AS5181 has separate analog and digital ground buses (AGND and DGND, respectively), the PC board should also have separate analog and digital ground sections with only one point connecting the two. Digital signals should AS5181 run above the digital ground plane, and analog signals should run above the analog ground plane. The device has two power-supply inputs: analog VDD (AVDD) and digital VDD (DVDD). Each AVDD input should be decoupled with parallel 10F and 0.1F ceramic-chip capacitors. These capacitors should be as close to the pin as possible, and their opposite ends should be as close as possible to the ground plane. The DVDD pins should also have separate 10F and 0.1F capacitors adjacent to their respective pins. Try to minimize analog load capacitance for proper operation. For best performance, bypass with low-ESR 0.1F capacitors to AVDD. The power-supply voltages should also be decoupled with large tantalum or electrolytic capacitors at the point they enter the PC board. Ferrite beads with additional decoupling capacitors forming a pi network can also improve performance. FIGURES 8A and 8B AS5181 Rev. 0.3 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 14 DA C Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* 24-Pin Flat Pack AS5181 (Package Designator F) *All measurements are in inches. AS5181 Rev. 0.3 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 15 DA C Austin Semiconductor, Inc. AS5181 ORDERING INFORMATION EXAMPLE: AS5181F-MIL Device Number AS5181 AS5181 AS5181 Package Operating Type Temp. F -* F -* F -* *AVAILABLE PROCESSES XT = Extended Temperature Range IT = Industrial Temperature Range MIL = Military Processing SPACE = Space Processing -55oC to +125oC -40oC to +85oC -55C to +125C -55oC to +125oC AS5181 Rev. 0.3 6/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 16 |
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